Asymmetric SRAM- Power Dissipation and Delay
Ashish Siwach, Rahul Rishi · 2011
In recent years rapid growth is noticed in mobile, hand-held communication devices, battery operated devices and fast data transfer demand, that these systems should have larger memory capacity and low power consumption with minimum operational delays. Since memory is main and consisting a large part of systems, nearly fifty percent, reducing the power and delay in memories becomes a hot burning issue. Almost half of the total CPU (central processing unit) dissipation is due to memory operations. It is necessary to identify the sources of power consumption and delay in memory blocks so that they can be reduced, hence allowing for better overall performance of the system. Today‟s microprocessors are very fast and require fast caches with low power dissipation and low delay. This paper presents the simulation results of 6T SRAM (six transistors static random access memory) cells, which are the main choice for today‟s cache applications. The stability of the cell is best among all the cells, existing in memory cell configurations.