Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits
Nagisa Ishiura, Mizuki Takahashi, Shuzo Yajima · 1989
As a new approach for timing verification of logic circuits, we propose a new concept of time-symbolic simulation. While a conventional symbolic simulator treats signal values as logical expressions, a time-symbolic simulator treats time as algebraic expressions. In this paper, we describe algorithms for time-symbolic simula tion, and its application to hazard detection and verification of asynchronous sequential circuits.