A VHDL Based Floating Point ALU for DSP Processing
K. Niranjan Reddy, D. Sri Harsha, S. Sri Vani, Shraddha Prasad · 2012
Many DSP techniques depend upon exclusive floating point arithmetic for the dynamic range of operations which require millions of calculations per second. Digital signal processing of 1d and 2d signals need different mathematical calculations which are mainly of complex data. Operations like FFT, Z Transform constantly requires various Exponential Arithmetic. Such computationally challenging techniques need computational acceleration using Custom Computing Machines (CCMs) being designed exclusively for the application. Floating point operations require excessive memory and time for conventional implementations. Therefore, custom formats for individual applications like DSP are more feasible on CCMs, and can be easily designed and implemented on a fraction of a single FPGA. VHDL, facilitates the design and development of custom operations without effecting the performance. Most of the processor architectures are built to handle real and non exponential data. Even though there are several architectures proposed over the years to explicitly handle exponential arithmetic, none are targeted for a specific DSP operation based on exponential arithmetic. In this paper we propose design of a unique exponential arithmetic unit for exponential addition.