Statistical analysis ofPowerDelayEstimation inaddercircuit using non-clocked passgatefamilies
Ajay KumarSingh · 2006
Inthepresent paper wehavedesigned a16-bit addercircuits withbasic passtransistor circuit approachand different topologyfor implementation. The proposedmultiplexing control input techniques oftheadder circuits are developed by thecarrysaveadder(CSA) technique. Thedifferent logic cells, usedfor various passgatescircuit designstyles are evaluated intermsofarea, propagation delay, powerdissipation andpropagation delay product. Thedesign styles arecompared byperforming detailed transistor-level simulations on a benchmark circuit (CSAadder) using DSCH3and Microwind3. We haveanalysed theresults ina statistical way.We havecompared ourresults with thevarious published results ofadder circuits .We found that thespeed oftheourproposed circuit is enhanced andpowerconsumption aswellasthe areahasreduced tremendously duetomultiplexing control input technique. Comparing thesimulated results withotherpasslogic designs, itwas observed thatinallexisting logic CPL isa promising candidate forfuture logic design.