SECTIONAL RECONFIGURABLE FIR FILTER DESIGN USING SYSTOLIC DISTRIBUTED ARITHMETIC (DA) ARCHITECTURE ON FPGA
Sk. Firoz, S. Girish Gandhi, C.Leela Mohan, M.Swarna Lakshmi · Indian Journal Of Applied Research · 2015
This work proposes an efficient architecture that employs a two dimensional fully pipelined structure to realize computationally efficient, low power, high speed Finite Impulse Response (FIR) lter. In distributed arithmetic, an architecture is dened for the LUT's (look up table) to reduce the partial reconguration time and this is stored in RAM. By changing the lter coeffi- cients in the partial recongurable module, the r lter is robustly recongured to achieve low pass and high pass lter characteristics. The proposed architecture shows improvement in reconguration time and efficiency. The design is implemented on Spartan3E FPGA kit.