IMPLEMENTATION OF 1024-BIT MODULAR PROCESSOR FOR RSA CRYPTOSYSTEM
Young Sae Kim, Woo Seok Kang, Jun Rim Choi · 2000
In this paper: an implementation method to optimize a 1024bit RSA processor is presented. Basically, the Montgomery algorithm is used and modiJied considering the latge bit modular multiplication. We propose a new architecture for 1024-bit RSA processing in order to reduce the required hardware resources. The new architecture is also fit for effective I/O interface. We have implemented a single-chip 1024-bit RSA processor based on the modtfied algorithm and architecture with 0.65-p SOG technology using verilog HDL. As a result, it is shown that the processor can perform 1024-bit RSA operation in less than 43ms at 50MHi.