Efficient Test Pattern Generation Scheme with modified seed circuit.
Payel C. Mukherjee · 2014
This paper proposes a modified test pattern generator which produces single bit change vectors so that switching activity is reduced which inturn helps to test an IC with minimum required power. Seed generator circuit has been modified which reduces the area overhead of test pattern generator(TPG) and makes its power efficient. The TPG is compatible with test per scan scheme. The paper has been implemented in cadence and all the necessary comparisons have been made. Circuits has been tested with test per scan scheme and necessary comparisons have been made to show reduction in power consumption and decrease in area overhead.