A Mixed Decimal/Binary Redundant Floating-Point Adder
Karim Yehia, Fathy Mahmoud, ElGhamrawy · 2011
Binary floating-point adders are used in processors to perform scientific computations. However, binary floating-point operations are not suitable for financial and commercial computations. Decimal floating-point operations were carried out in software until recently when IBM introduced decimal floating-point adders in their z9 and z10 processors. In this research, initially a decimal floating-point adder is proposed. The floating-point numbers are encoded in a redundant format. The digit set is [-6, 6]. Redundancy allows for a carry-free addition so that the addition operation does not depend on the width of the operands. The adder was synthesized with the TSMC 65 nm LP technology and shows a latency of 2.02 ns (48 FO-4) and a total area of 24683 um 2 . The design is then extended to incorporate IEEE-compliant binary addition as well. This preserves the speed gains produced through redundancy while using the same hardware resources for both binary and decimal operations. Synthesis Results show a 68% increase in delay over the decimal one, and a 26.8% increase in area. This makes our mixed floating-point adder more area-efficient to rather than using a separate binary floating-point adder and another separate decimal one. The Mixed floating-point Adder was further pipelined into five stages to increase the maximum frequency of operation, and to allow for overlapping the execution of binary operations and decimal ones. Synthesis results show that our pipelined mixed floating-point adder can operate on a clock with a frequency up to 1.04 GHz.