to Instruction-Based Test Generation for Modules of VLSI Processors
Kazumi Hatayamal, Takeshi Miyazaki, Hiromichi Yamada · 1997
'This paper presents a practical approach to functional tes>t pattern generation for gate level faults in functional modules of VLSI processors. Test patterns are generated by constrained test generation and translated to functional testpattems, each of which is a sequence of instructions. ,In this paper, the outline of instruction-based test generation system, ALPS, is given first, and then constrained test generation is described in detail. Finally, the result of practical application to a VLSI processor is given to illustrating the effectiveness of our approach.