SPI Configuration and Flash Programming in UltraScale FPGAs
Matt Nielson, Ryan J Rumsey · 2015
Summary This application note describes the UltraScale™ FPGAs master serial peripheral interface (SPI), 4-bit datapath (x4 or quad) configuration mode. The x4 mode is recommended, but the 1-bit datapath (x1) and 2-bit datapath (x2) modes are easily adapted from the x4 mode if needed. The application note reviews the basics of master SPI configuration that can aid in successful SPI configuration and debugging of configuration during initial design bring-up. This document also includes instructions for generating a bitstream for SPI configuration and programming this bitstream into the SPI memory device using the Vivado® Design Suite Integrated Design Environment (IDE) as well as a Tcl flow that can be used from the command line. A sample set of connections between the SPI memory device and the FPGA required for master SPI x4 are also provided.