and Performance of a New Arithmetic Computation of Elementary Functions
R. A. Meyer, R. Mehling · 1990
The design of a recursive arithmetic unit for the evaluation of elementary functions is discussed. Two distinct classes of binary algorithms are implemented. One class is based on a generalization of the “compensated CORDIC method”. The other class, which replaces the linear CORDIC case, is based on convergence transformations in connection with multiple bit encoding techniques. The proposed hardware solution provides a significant speed advantage over software calculations and more flexibility than special units designed only for a subset of these functions. 1. STATEMENT OF THE PROBLEM During the past few years, programmable digital signal processors (DSP) have undergone a rather rapid development. In addition to the trends of increased on-chip memory size and speed, and of the transition from fixed-point to floating-point arithmetic, a continuous architectural improvement has taken place to enhance system performance. The architecture as well as the instruction set have been improved now such that the throughput of the arithmetic unit equals the maximum throughput of data for many algorithms, if multiplication and addition are the only operations needed. However, a large variety of other useful signal processing algorithms, particularly for adaptive filtering, matrix algebra and SVD, also contain a significant number of more complex operations such as vector rotations, square roots, divisions, and transcendental functions. The execution time of these operations is long, compared with the execution time of multiplication and addition. Table 1 shows assembly-language benchmarks in terms of instruction cycles for some DSP chips, using floating-point arithmetic with a 24-bit mantissa and an 8-bit exponent.