SESSION XVI: VLSl LOGIC
Bernard T. Murphy, R. V. Edwards, Lee C. Thomas, John J. Molinelli · 1980
A FULL 32b CPU* implemented in CMOS using a latch-up free twin-tub technology”L will be described, citing the architecture from both the user’s external and internal hardware viewpoints. From the user’s viewpoint the CPU supports efficient compilation of high level languages with respect to both code space and execution time. In addition, it has features which support the design of an operating system. The instruction set is orthogonal so that any opcode can be used with any operand descriptor. The CPU can handle data of many types including words (32b), half words (16b); and bytes (8). Some instructions handle bit fields and blocks as well. The addressing modes are quite extensive and are indicated in Table 1. The instruction set is very effective at data manipulation. For example, a single instruction can move blocks from memory to memory, or push and pop a group of registers with respect to the stack.