A Novel ardware Accelerator Architecture for MPEG2 4 AAC Encoder
Yan-Chen Ly, Chm-Fu Shen, Chi‐Kuang Chen · 2004
A V SI architecture of MPE -2 AAC encoding accelerator is proposed. This hardware IP ir an AMBA AHB peripheral component that can easily mtegrate with any other RISC based SoC platform. Preseming theflexibility of lihrary drvelopment andachieving an area cost-efficient acceleration, the quanti ation rateloop module is targeted to be the processing function. Among the design, an easy tfuflan codebook search methodis also developedfor the viability of hardware reali ation. The final work has been verified in an FP A and synthesi ed to a 0. I um standard cell library. It can speed up an audio recording application by 1. -time and achieve a real-time encoding for stereo .I H PCM data with additional 0 MH ARM power.