Testing for Parametric Faults Circuits
Joel Ferguson, Martin Taylor, Tracy Larrabee · 1990
Many defects causing bridges, breaks, and transistor stuckons in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. These undetected, non-traditional faults may be detected as increased propagation time or as excessive quiescent power supply current (IDDQ). In this paper we compare the cost of testing for excess IDDQ caused by bridge, break and transistors stuck-on faults versus the cost of traditional testing methods.