Enabling testability of fault-tolerant circuits by means of I/sub DDQ/-checkable voters
Alessandro Bogliolo, Michele Favalli, M. Damiani · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2000
The reliability of a fault-tolerant circuit may be drastically impaired by the presence of maskable faults that never affect its functionality. Design for testability (DFT) techniques have to be applied to make maskable faults detectable. During the testing phase, traditional DFT schemes inhibit fault masking and/or activate additional observation/control paths through the circuit. Such schemes, however, do not enable on-line testing and cannot be applied to multilevel fault-tolerant circuits, where fault-masking is repeatedly performed inside the circuit. We propose a new approach to the design of testable fault-tolerant CMOS circuits that overcomes both limitations. Our approach is based on the use of I/sub DDQ/-checkable voters (ICVs) that enable a complete test of maskable faults of any multiplicity during normal operations.