Efficient FPGA-Based Multipliers for F397 and F36.97
Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann · 2007
In this work, we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier, in which the area of the digit-multipliers is reduced using the Karatsuba method. We compare our results with the other works of the literature for F397. Furthermore, we propose new formulas for multiplication in F36.97. These new formulas reduce the number of F397-multiplications from 18 to 15. The finite fields F397and F36.97are important fields for pairing based cryptography.