ADDITIONAL DEVELOPMENTS IN EMBEDDED COMPUTER PERFORMANCE MEASUREMENT Diane Kohalmi and John Newport, Ph.D. Naval Avionics Center
D. Paul, C. Roark, David G. Stroble · 1992
This paper reports on the results of Phase II of the Advanced Avionics Technology Demonstration (AATD) Embedded Computer Performance Measurement (ECPM) Program performed by Texas hstruments 0 for the Naval Avionics Center (NAC). During the first phase of the AATD program which began in June 1990, a novel method was developed for measuring spare processor and I/O throughput reserves. These measurements are typical of those required by Navy standards such as the Tactical Digital Standard (TADSTAND-D). The Phase I work was based on a 16-bit MILSTD-175OA processor embedded in the TI Mission Display Processor (MDP) developed for the DEM/VAL phase of the YF-22 prototype. During Phase 11, additional experiments were conducted using the MDP to host the ME’S R3000 Reduced Inshruction Set Computer (RISC) and TI TMS320C30 signal processor. This paper reports on the results of those experiments and summarizes important lessons learned during the AATD program.