Design and Implementation for 8 bit Double Harvard core processor for small scale systems
Pulkit Trivedi, Deepak Asati · 2012
The concept of this paper comes after mulling over all CISC and RISC processor implementation and we are proposing a new microprocessor architecture which will have CISC type instruction set (large instruction set good for multiple applications) and RISC type feature for executing every instruction in one cycle. To achieve these we just exclude few instructions (total five) of CISC. Though still we have covered all small scale and medium scale applications with our proposed architecture on cost of nothing and all sophisticated scale application on cost of extra few nanoseconds.