Implementation Of Floating-point Adder Unit
K Gayathiri, Surya Prakash, S. Valarmathy · 2014
Abstract— Floating point is the most important part of many modern microprocessor. It is complex while using butterfly structure for large bit of floating point representations. For a radix implementation, it consists of complex butterfly structure followed by complex part of addition and subtraction. Thus, these complex butterfly operations can be implemented with a fused add subtract unit. IEEE 754 standard specifies the methods for binary and decimal floating point arithmetic unit. Moreover, single precision addition and subtraction is performed by normalization. The numerical result of the fused butterfly unit is more accurate because only fewer rounding operations are used compared to conventional floating point. In this paper, add/subtract unit is implemented using vhdl language and simulation are verified. Index Terms— add/subtract unit, IEEE 754, normalization, single precision.