ARCHITECTURES BASED ON LNS
Giorgos M. Papadourakis, John P. Condorodis · 1988
The design and development of a processing element (PE), in an orthogonal systolic architecture, using the state of the art in VLSI technology, will be presented. The goal was to create a high speed, high precision PE which would be adaptive to a highly configurable systolic architecture. In order to achieve the necessary computational throughput, the arithmetic unit of the processing element was implemented using the Logarithmic Number System.