Design and Implementation of Floating Point Multiplier Using Wallace and Dadda Algorithm
Chaitali V. Matey, Swapnil Chede, Shruti Sakhare, Student M. Tech, Suresh Deshmukh · 2014
In computing, floating point describes a method of representing an approximation of a real number in a way that can support a wide range of values. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. This paper presents a floating point multiplier using Wallace and Dadda Algorithm of an IEEE 754 single precision floating point multiplier targeted for Xilinx. Improvement in speed multiplication of Dadda and Wallace multiplier is done thereby replacing Look ahead Carry adder. The methodology uses Exponent Calculator, Mantissa multiplier, Sign Calculator, and Normalization unit.