Decimal Addition and Subt" - unitsusing the pvalued Decimal Signed-Digit Number Repn%sentation
Noriaki Muranaka, Shigeru Imanishi, D. M. MiUer · 1993
For the addition and subtraction of two numbers in conventional representations, the worst case time delay is proportional tv the number cd digits. Par- addition and subtraction a€ two numbers with signed-digit number representation can be performed in constant time. In this paper, we present a signed-digit represen tation for radix r = 10 (SDlOR), and we wnsider the usefulness a€ asymmetnbl SDlOR. Further., we pmm p(qk-. q1)-valued SDlOR's in which p is represented as a combination of qk to ql. We also describe a p(q2ql)-valued SDlOR addition and subtracrhbn unit, in which p is large. Finally, we present and compare simulation data for &pi& SD1 OR's.