ARCHITECTURE EXPLORATIONS FOR ELLIPTIC CURVE CRYPTOGRAPHY ON FPGAS
Chester Rebeiro · 2008
The current era has seen an explosive growth in communications. Applications like online banking, personal digital assistants, mobile communication, smartcards, etc. have emphasized the need for security in resource constrained environments. Elliptic curve cryptography (ECC) serves as a perfect cryptographic tool because of its short key sizes and security comparable to that of other standard public key algorithms. However, to match the ever increasing requirement for speed in today’s applications, hardware acceleration of the cryptographic algorithms is a necessity. As a further challenge, the designs have to be robust against side channel attacks. This thesis explores efficient hardware architectures for elliptic curve cryptography over binary Galois fields. The efficiency is largely affected by the underlying arithmetic primitives. The thesis therefore explores FPGA designs for two of the most important field primitives namely multiplication and inversion. FPGAs are reconfigurable hardware platforms offering flexibility and lower costs like software programs. However, designing on FPGA platforms is challenging because of the large granularity, limited resources, and large routing delay. The smallest programmable entity on an FPGA is the look up table. The arithmetic algorithms proposed in this thesis maximizes the utilization of LUTs on the FPGA. A novel finite field multiplier based on the recursive Karatsuba algorithm is proposed. The proposed multiplier combines two variants of Karatsuba, namely the general and the simple Karatsuba multipliers. The general Karatsuba multiplier has a large gate count but for small sized multiplications is compact because it utilizes LUT resources efficiently. For large sized multiplications, the simple Karatsuba is efficient as it requires lesser gates. The proposed hybrid multiplier does the initial recursion using