BIST Controller Design to Monitor Fault Detection Activity with Hold Logic and a Signature Generation Element
M. Tech · 2013
Today Field Programmable Gate Arrays (FPGAs) are widely used in many applications. These FPGAs are prone to different types of faults similar to other complicated integrated circuit chips. Faults may occur due to many reasons like environmental conditions or aging of the device. The rate of occurrence of permanent faults can be quite high in emerging technologies, and hence there is a need for periodic testing of such FPGAs. The Configurable Logic Blocks (CLBs) are the main logic resources for implementing sequential as well as combinatorial circuits. Built-in self-test (BIST) is a design technique that allows a circuit to test itself. It is a set of structured-test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks. BIST controller coordinates the operations of different blocks of the BIST. BIST controller is designed to work in different modes. Here, we introduce a new approach for FPGA testing that exploits the reprogrammability of an FPGA to create the BIST logic by configuring it only during off-line testing. In this way, testability is achieved without any overhead, since the BIST logic disappears when the circuit is reconfigured for its normal system operation. We are implementing a restartable logic BIST controller for the configurable logic blocks in FPGAs by using the resources of FPGA itself. We have used XILINX ISE13.2 for simulation and synthesis. Key terms: FPGA, SRAM, CLB, external Flash memory chip, SRAM configuration cells, Complex programmable logic devices, Antifuse-based FPGAs, BIST, Spartan3E.