Implementation of Floating Point Divider for Interval Arithmetic
Tejas V. Shah, Deepali H. Shah, Control Dept · 2011
Interval arithmetic provides an efficient method for monitoring and controlling errors in numerical calculations and can be used to solve problems that cannot be efficiently solved with floating-point arithmetic. However, existing software packages for interval arithmetic are often too slow for numerically intensive calculations. While conventional floating point arithmetic is provided by fast hardware, interval arithmetic is simulated with software routines based on integer arithmetic. Therefore, the hardware design for interval arithmetic can provide a significant performance improvement over software implementations of interval arithmetic. In this paper, we design interval divider unit that performs as either interval or floating-point divider. This unit requires slightly more area than a conventional floating point divider. It provides a significant performance improvement over software implementations of interval divider. The unit is implemented in Verilog and synthesized to estimate the area and the worst case delay. The goal of the divide-add fused unit is to increase the performance of the interval Newton’s method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.