An Analytical Approach to Direct IP Protection of
Debasri Saha, Susmita Sur‐Kolay · 2008
In the DSM VLSI technology, wide-spread design reuse to meet customer's requirements in time enhances the probability of infringement of Intellectual Property (IP) of VLSI physical design. In design storage or during design transmission between two parties, encryption of a design file is a well- known technique to protect a design against hacking, although it takes significantly long time to encrypt large design files. While encryption basically substitutes and shuffles the bits/ASCII values of a file to conceal the contents of the file, the IP value of a design obtained from optimized partitioning, floorplanning and placement can be protected by redistribution of design elements in the modules and exchanging the locations and orientations of the design modules. As security of design through perturbation exploits the basic properties of physical design, this technique is applicable to protect any intermediate phase, not restricted to binary/ASCII GDSII/OASIS file format only. In this paper, encoding moves for various floorplan representations are analyzed in terms of their time and space requirements. Experimental results on MCNC benchmarks are encouraging. With the enhancement of integration in VLSI technol- ogy, design complexity of integrated circuits is increasingly growing. In that context, demands for higher productivity in shorter time mandate design reuse. The circuit components in a design, now available in electronic form and known as virtual components, signify intellectual property (IP) of the design. The risk of any misuse of design IP emphasizes the need of intellectual property protection (IPP) of VLSI design. Techniques to protect IP of VLSI design can be of two types — direct and indirect. Protection of designs either in repos- itories or during web transmission is enforced through direct IP Protection whereas detection of any misappropriation of design IP through embedding of watermarks and fingerprints into the design to identity the legal owner and the buyer of the design, is discussed under indirect IPP. In this paper, we propose a novel technique for direct IP protection of VLSI physical design. Frequently updated versions of design tool and enhanced loss due to design tool misuse encourages us to transmit design only instead of design tool. Due to high risk of being hacked, the entire design file should be encrypted when the high quality design is transmitted from IP owner to buyer, in electronic form either