Virtex-5 Based Delay Study and Realization of Braun's Multipliers
Muhammad Haris Rais, Mohammed H. Al Mijalli, Saudi Arabia · 2012
Abstract: In this study we investigate the delay, design and implementation of Braun’s multipliers using Very High speed integrated circuit Hardware Description Language (VHDL) and implemented on Virtex-5 field programmable gate array (FPGA) devices. The Virtex-5 FPGA devices including XC5VLX30, XC5VLX30T, XC5VLX50, XC5VLX50T, XC5VLX85 and XC5VLX85T and their resource utilization is obtained for 4×4, 6×6, 8×8 and 12×12 Braun’s multipliers. The delay study was analysed using analysis of variance (ANOVA) method using the software Statistical Package for Social Science (SPSS) with a 0.05 confidence level was used to compare the FPGA Virtex-5 devices. The comparison between Virtex-5 devices show same numbers for four input LUTs, bonded IOBs, total equivalent gate count but their occupied slices, average connection and maximum pin delays are different. The delay study comparison test shows that the differences between the FPGA Virtex-5 devices are insignificant.