Implementation Of A RS Decoder Architecture using Artificial Neural Network
Mrinmoy Sandilya · 2013
In this paper, an architecture for a typical Reed Solomon Decoder using Artificial Neural Network is presented. Reed Solomon codes are extensively used burst error correcting codes, used in applications like error correcting of data in CD/DVD, error correcting of faulty data read out of a bar code, and also in fields like data transmission such as DSL and WiMAX and satellite transmission. These are cyclic BCH (Bose-Chodhuri-Hocquenghem) codes but unlike BCH codes Reed Solomon codes are non binary codes . The architecture of a typical Reed Solomon encoder and decoder uses concepts of Finite fields and Galois field operations from abstract algebra extensively. Choosing the right methods of realizing Galois field operations play a crucial role in efficient realization of a Reed Solomon Decoder hardware in terms of circuit complexity and time complexity. This paper explores the possibility of incorporating the concepts of Artificial Neural Network in realization of Reed Solomon Decoder architecture in an attempt to reduce the complexity. An artificial neural network is a massively parallel network of artificial neurons capable of parallel computations. The implementation of syndrome block is done with HDL synthesis report (Macro statistics count of 4 3-bit registers, 121 XOR-2 gates) in Xilinx ISE project navigator.