Minimizing switching activities through reordering algorithm for efficient power management
A. L. Kavitha, S. Sasikumar · 2014
One of the emerging challenges in the current scenario of modern-day technologies is the power dissipation occurring in high end VLSI circuits that are predominantly caused due to the switching activities of the circuit under test procedures. We have presented a well-organized test pattern generator that is more appropriate for built in self-test (BIST) structures used in the testing of VLSI circuits. The BIST sufficiently keeps the power dissipation in check without altering the fault coverage. Our version of the test pattern generator aims at bringing down the switching activity to the least minimum amount possible. In addition to this, a modified version of Floyd algorithm is used which re-orders the vectors in the test sequence and this further reduces the switching activities that occurs while testing of combinational circuits. This technique brings down the hamming distance between test vectors which leads to reduction in dynamic power dissipations to a great extent. Moreover, in order to reduce execution time and power, genetic algorithm is incorporated with Floyd algorithm. We have used the ISCAS’85 benchmark circuit for our experiments.