Built-In Self-Test for Digital Signal Processor Cores in Virtex-4 and Virtex-5 Field Programmable Gate Arrays
Mary D. Pulukuri · 2010
Current Field Programmable Gate Arrays (FPGAs) incorporate special cores, apart from logic, such as digital signal processor (DSP) cores. The DSP cores can be cascaded to implement complex functions. An effective test approach for testing the logic and configuration memory associated with these embedded cores is essential. The thesis presents an effective approach for testing digital signal processor cores embedded in Virtex-4 and Virtex-5 FPGAs using Built-In Self-Test (BIST) methodology. Since the BIST circuitry can be programmed in the logic present inside the FPGA that is not being tested at the time, there is no area overhead or performance penalty. The implementation and verification of the developed BIST configurations was done on various families and sizes of Virtex-4 and Virtex-5 FPGAs. The developed BIST configurations also detected manufacturing faults in some of the Virtex-4 engineering sample parts. ii Acknowledgements I would like to thank Dr. Stroud for his guidance and support throughout my research for my thesis. I am grateful for his teaching that trained me to be a better engineer. I would like to thank Dr. Singh, Dr. Nelson and Dr. Agrawal for serving on my committee and for their helpful suggestions in improving my thesis. I would like to thank my colleagues Brad, Joey, Jie and Alex for their valuable advice and support.