Development of Parallel Queue Processor Architecture and its Integrated Development Environment
Hiroki Hoshino · 2011
The high performance processors have been required long time. The instruction level parallelism (ILP) is one of the important essences to enable processors to be high performance processors. There are two main techniques to exploit ILP, VLIW and superscalar. The complex compiler to generate the VLIW instruction is needed in the aspect of software. The superscalar scheme needs large area for the finding ILP with big instruction window and register renaming techniques. The queue instruction set processor architecture is the approach to get ILP with simple techniques. The intermediate results are saved in the queue register, which follows the first-in first-out rule, instead of the random access register. The instruction reads the operand from the head of the queue register implicitly. The execution result is written into the tail of the queue implicitly. There is no need to specify the register number in the instructions. The instructions for the queue processor are generated by traversing the data acyclic graph in level order manner. There are promising advantages in the queue processor; high ILP and short instruction width. In this thesis, the superscalar, out-of-order, produced order parallel queue processor (QC-3) is designed. The design is implemented by Verilog-HDL to get high accurate evaluation result with synthesis tools provided by a company. And also the queue compiler, the assembler and its simulator are proposed. These design suites are useful to design the programs for the queue processor. Chapter