Reducing the cost of massively parallel, very high speed computing: A heterogeneous hybrid solution
Iain S. Elliott · The UNSW Canberra at ADFA Journal of Undergraduate Engineering Research · 2013
As data sets become exponentially larger and scientific computing problems more complex, the ability to analyse and solve them relies more and more on high performance computing (HPC) solutions. Traditional methods of HPC involving parallelising multiple microprocessors has seen a dramatic increase in computing power available to scientists and engineers. These systems, however, can require vast amounts of power to both run the compute engine and remove excess heat generated by the injection of that power. The search for higher performance systems with lower power consumption has recently led to great interest in hybrid systems comprising hardware accelerators such as field programmable gate arrays (FPGAs) and general purpose graphical processing units (GPUs). The low power consumption and inherent re-configurability of FPGAs and dense matrix floating point capabilities of GPUs have made them ideal candidates for hardware acceleration. This paper presents a heterogeneous, CPU/GPGPU/FPGA hybrid, desktop computing system (the “Chimera”). This system is built using commercial-off-the-shelf components and provides a low-cost, reconfigurable solution to today’s scientific computing requirements capable of achieving energy savings 4 orders of magnitude greater than CPU only machines and 3 orders of magnitude greater than comparable GPGPU/CPU solutions for the same compute output.