Hardware-based temporal logic checkers for the debugging of digital integrated circuits
Jean-Samuel Chenard · eScholarship@McGill (McGill) · 2012
Integrated circuit complexity is ever increasing and the debug process of modern devices pose important technical challenges and cause delays in production. A comprehensive Design-for-Debug methodology is therefore rapidly becoming a necessity. This thesis presents a comprehensive system-level approach to debugging based on insilicon hardware checkers. The proposed approach leverages existing assertion-based verification libraries by translating useful temporal logic statements into efficient hardware circuits. Those checker circuits are then integrated in the device as part of the memory map, so they can provide on-line monitoring and debug assistance in addition to accelerating the integration of performance monitoring counters. The thesis presents a set of enhancements to the translation process from temporal language to hardware, targeted such that an eventual debug process is made more efficient. Automating the integration of the checker's output and control structures is covered along with a practical method that allow transparent access to the resulting registers within a modern (Linux) operating system. Finally, a method of integration of the hardware checkers in future Network-on-Chip systems is proposed. The use of a quality metric encompassing test, monitoring and debug considerations is defined along with the necessary tool flow required to support theprocess.