Preternatural Low-Power Reversible Decoder Design in 90 nm Technology Node
Neeraj Kumar Misra, Subodh Wairya, Abdhesh Kumar Singh · 2014
In Low Power VLSI Technology IC designers have encountered more constraints High speed, Small silicon area, and High throughput and Low Power dissipation. Designer is faced problem for this issue and technology doesn't advance at the same rate. Reinvent a design for Building a great interest. Reversible logic gives a solution for this issue because it has ideally zero power consumption and prevents the loss of information which is the root cause of power dissipation. In this way and optimized low power decoder and two New high speed Reversible Gates 'RG_1' and 'RG_2'are proposed by connecting this improvement of power dissipation. An epitome design methods is Reversible Gates, in reversible the number of inputs is equal to the number of outputs, allow for prevision of all succeeding states based on known retiring state, and the system ambit every potential state, termination is no heat dissipation. In this paper synthesis the reversible decoder using Xilinx platform and operative coded design is to be simulated on simulation software (e.g.Isim). Employed properly for dynamic input befitting output obtained and also reversible decoder is compelled on MOS synthesis using Tanner14 EDA tools