A Universal VLSI Architecture for Reed-Solomon
Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen‐Yi Lee · 2009
This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syn- drome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After imple- mented with 0.18- m 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm silicon area, and the average core power consumption is 68.1 mW. Index Terms—Error-and-erasure correction, Montgomery mul- tiplication, Reed-Solomon (RS) code, universal architecture.