IENTED TEST TECHNIQUE FOR VLSI'S USING ATE
Yasuji Oyama, Toshinobu Kanai, Hironobu Niijima · 1996
A new test technique to localize failures of devices with scan design easily and quickly using LSI tester is proposed. This technique allows device designers or test engin- to localize the scan Flip Flops that failed Using expressions based on the scan design of the device. These devices are defined by the Boundary Scan Description Language (BSDL) or an extension to BSDL proposed in this paper, This technique can be applied to standard boundary scan designs and to ad-hoc internal scan implementations. Furthermore. restrictions ftom limited tester resources has been solved by technique. As a result, it is possible to speed-up of the failure analysis resulting in a decrease of the test costs.