Garp's on-chip, reconfigurable coprocessor was tailored specifically for accelerating loops of general-purpose software applications. Its novel features inspired a unique approach to automatic compilation from C.
J Norman Timothy, Robert John · 2000
arious projects and products have beenbuilt using off-the-shelf field-programma-ble gate arrays (FPGAs) as compute accel-erators for specific tasks. Such systemstypically connect one or more FPGAs to thehost computer via an I/O bus. Some have shownremarkable speedups, albeit limited to specific appli-cation domains.Many factors limit the general usefulness of such sys-tems. Long reconfiguration times prevent accelerationof applications that spread their time over many differ-ent tasks. Low-bandwidth paths for data transfer limitthe usefulness of such systems to tasks that have a highcompute-to-memory-bandwidth ratio. In addition, stan-dard FPGA tools require hardware design expertisebeyond the knowledge of most programmers.To address the bandwidth problems, some devel-opers have proposed integrating specially designedrapidly reconfigurable hardware more closely with theprocessor. To help investigate this idea we designedour own architecture in detail, called Garp,