TheImplementation ofDigit-Serial FIRFilters Based onFPGA
Shuqin Lou · 2005
BasedonFPGA,a digit-serial FIR Inthispaper, digit-serial algorithm moduleis filter isimplemented. According tothedigit-serial usedinbit-serial FIRfilter inorder toavoid the algorithm, thedigit-serial FIRfilter iscomposeddisadvantages oflowspeed inthebit-serial offoundational function modules including the algorithm module andhigh hardware consumption digit-serial adder, thedigit-serial multiplier and inthebit-parallel algorithm module. Atthesame thedelay circuit. Compared withthetraditional time, this paper offers anefficient solution ofthe method, thedigit-serial FIRfilter based onFPGA balance amongspeed, areautilization, throughput, exhibits theadvantages ofhighresponse speed I/Opinlimitations andpowerconsumption. andlowhardware consumption. Furthermore, the 2.Digit-serial Algorithm Module relationship between thespeedandtheareais adjusted inabetter manner inthedigit-serial FIR Inadigit-serial algorithm, theW bits ofadata filter. Thedigit-serial FIRfilter withN=2hasthe wordareprocessed inunits ofthedigit-size N inP minimum ofarea-time product. clock cycles that isequal toW/N.Oneindependent