VLSI Implementation of a Realtime
Roberto Y. OMAKIt, Morgan H. MIKIt · 2000
The architecture of a realtime wavelet video coder is described, with main emphasis put on memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2-D subband decomposition scheme, alongside of a parallelized pipelined Em- bedded Zerotree Wavelet coder architecture. The video encoder is integrated in a 0.35 pm 3LM chi by using 341 K transistors on a 4.93x4.93 mm die, which can process 720x480 3Ofps pictures in realtime.