ALowPower128-pt Implementation ofFFT/IFFT for HighPerformance Wireless Personal AreaNetworks
Jimson Mathew, Koushik Maharatna, Dhiraj K. Pradhan · 2006
A novelarchitecture forlowpower128-pt FFT/IFFT processor forapplication inIEEE802.15.3a standard design is proposed, wherethe128-pt FFTisdevolved into8-ptand16-pt FFTsandthenonceagain bydevolving the16-pt FFTinto4x4 and2x8.Theanalysis demonstrated thatwithmodestincrease inareaonecanachieve significant reduction inpower.The proposed architectures complete oneparallel-to-parallel (i.e., whenallinput dataareavailable inparallel andalloutput data aregenerated inparallel) 128-pt FFTcomputation in312ns. The relative merits anddemerits ofthesearchitectures havebeen analyzed fromthealgorithm aswellasimplementation point of view. Detailed poweranalysis ofeacharchitecture atblocklevel isdescribed. Frompowerperspective thesecond architecture is better, however boththearchitectures givesignificant reduction ofalgorithmic complexity compared totheexisting schemes. For thesecondarchitecture thecorepowerconsumption isonly 72mw.Apartfromthelowpowerconsumption, theadvantages of theproposed architecture include reduced hardware complexity, regular dataflowandsimple counter basedcontrol.