Media processor core architecture for realtime, bi-directional MPEGB(H.26X Codec with 30 fr/s for CIF-video
Ofuna Kamakura · 2000
We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 frls. The core processor contains 6.3 M-transistors on only 14mm2 silicon area and consumes 280mW at 1.8V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and a 2-dimentional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively.