RUN-LENGTH BASED COMPRESSION FOR SELECTIVE UNSPECIFIED TEST PATTERN
S. Saravanan, A. Balasubramaniyan · 2012
In all System-on-a-Chip (SoC) designs, there is a necessity to reduce the large test data volume and this is achieved by test data compression. One of the methods is the variable-to-variable length compression method. A selective run-length based compression which comes under variable-to-variable method is presented in this paper. The proposed work is based on threshold calculation on don’t cares (X). So compression is not targeted for all the test patterns. Depending upon threshold value compression is identified. The test patterns having large number of don’t-cares (X’s) are selected for compression. Also the test vectors having less compression ratio is not considered for compression by calculating its threshold value. The selected test patterns can be divided into number of blocks containing equal number of test vectors. Each block is compared with the adjacent blocks bit-by-bit and it has to be merged. The number of blocks merged can be given in the control code. The experiments are conducted on ISCAS’89 benchmark circuits to know the effectiveness of the compression technique. The results show that the technique has a reasonable effect on compression.