High Speed and Low Power Implementation of FIR Filter Design using DADDA & WALLACE Tree Multiplier
Jami Venkata Suman · 2014
The most area consuming arithmetic operations in high-performance circuit's Finite Impulse Response (FIR) multiplication is one. We are using different types of multipliers to reducing the cost of effective parameters in FIR filter design. We use only truncated multipliers in design, by using these multipliers we consume some more area and power, and ineffective results in transposed form. The structural adders and delay elements occupies more area and consumes power in these form so it was a reason to forward the proposed method. In prior FIR filters design with low cost effective results will done by the faithfully rounded truncated multipliers with the carry save additions, In direct form of FIR filter we use MCMAT for multiplication and accumulation operations. With compare of previous designs in direct form we reduce the area while decrease of the full adders, half adders and registers. In MCMAT and design the low cost FIR filters within the best area and power results we implement these improved truncated methods.