Reconfigurable Systolic Array Implementation of
M Van Pee, Pramod P. Khargonekar, E. Bruce Lee, Hsing-Hsing Chiang, Chrysostomos L. Nikias, A.N. Venetsanopoulos · 1986
B( zl, z2) = 1 - z2 + 0.22; - 0.5~~ + 0.8~~~~ Abstract -In this correspondence, we present a new reconfigurable implementation structure for quadratic digital filters using systolic arrays. The structure is based on matrix decomposition realizations and exhibits high parallelism, great modularity, and regularity. It is flexible enough to accommodate any quadratic filter of a given order and rank, just by opening a number of switches and tuning a set of parameters at each active module.