Efficient Test Pattern Generator for BIST using Multiple Single Input Change Vectors
I D. Punitha, Sudheesh Kumar · 2014
Digital circuit’s complexity and density are increasing while, at the same time, more quality and reliability are required. These trends, together with high test cost, make the validation of VLSI circuits more and more difficult. This paper proposes a novel test pattern generator (TPG) for built-in self-test. Our method generates multiple single input change (MSIC) vectors in a pattern, i.e., each vector applied to a scan chain is an SIC vector. According to the different scenarios of scan length, this paper develops two kinds of SIC generators to generate Johnson vectors and Johnson codeword’s, i.e., the reconfigurable Johnson counter and the scalable SIC counter. The proposed TPG is flexible to both the test-per-clock and the test-per-scan schemes. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. Analysis results have the favourable features of minimum transition of sequence, uniform distribution of pattern, uniqueness of pattern, and low hardware overhead.