Interface Design forHardware-in-the- Loop Simulation
Martin Schlager, Wilfried Elmenreich, Ingomar Wenzel · 2006
Thispaperpresents ascalable approach tointer- facebetween atime-triggered distributed hardware-in-the- loop(HIL)simulator andthesystemundertest(SUT)via SmartVirtual Transducers (SVTs). AnSVTisanelement ofanHILsimulator andimplements twointerfaces -astan- dardized digital interface toatime-triggered transducer net- workandatransducer-specific interface. Themaincontribution oftheapproach isaseparation ofthe execution ofthesimulation modelandthedeterministic in- teraction viaanarbitrary transducer interface. Thebenefit ofsuchseparation isthetemporal decoupling between sim- ulation modelexecution andinteraction withtheSUT.Fur- thermore, theapproach leads toareduction ofcomplexity of thesimulation setup. Theapplication oftheapproach isshownbyanSVTproto- typethatisusedtosimulate atemperature sensor.