Variable-Packet-Size Buered Crossbar Switch Chip
Dimitrios G. Simos · 2004
Switches and routers are the basic building blocks of most modern interconnections and of the Internet, aiming at providing datapath connectivity, while solving output contention, the major problem of distributed, multi-party communication. The latter is accomplished through buering, access control, o w control, or datagram dropping. Modern high-end switches are called upon to provide aggregate throughputs in the terabit per-second range, which greatly challenges both their architecture and implementation technology. The aim of this work is to prove the feasibility of a novel buered crossbar organization, operating directly on variable-size packets. Such operation, combined with distributed scheduling, removes the need for internal speedup, thus fully utilizing the incoming throughput. We proved the feasibility of this novel architecture by fully designing such a 32x32 buered crossbar, in the form of an ASIC chip core, providing 300 Gbit=sec of aggregate bandwidth in 0.18 m technology, or higher throughput in more advanced technologies. The design was synthesized, placed, and routed, using a hierarchical ASIC o w, resulting in a 420 mm 2 , 6 Watt core in 0.18 m CMOS technology. In 0.13 m CMOS, area would be reduced to 200 mm 2 , and power consumption to 3.2 W. Power estimation showed that the majority of power is consumed in driving cross-chip wires, while memories and logic are minority consumers. Hierarchical ASIC o ws are dicult to use, but became necessary due to the large size of the design. We present the detailed system design (block diagrams as well as critical circuit details), followed by a detailed description of the design o w, including its numerous intricacies and the lessons that we learnt. In particular, we describe the choice of a hierarchy that is appropriate for eectiv e placement, routing, and timing behavior. The nal placement and routing showed that the synthesis tool had underestimated the design area by 30%, due to the dominance of long (end-to-end) wires in this design.