VLSI ARCHITECTURE FOR LOW POWER MINIMUM SIGNED DIGIT MULTIPLIER FOR FIR FILTER AND ITS SIGNAL PROCESSING APPLICATIONS
V. Sumathy, E. J. Aishwarya, Snekalatha Saravanakumar, M. Gayathri Devi · 2012
Most of the Digital Signal Processing applications (DSP) involve multiplication and accumulation operation. As multiplier decide the critical computation time and power dissipation of a signal processing architecture, design of high throughput and power efficient multiplier is a major challenge. In this paper, we proposed a new architecture for high speed multiplication based on shifting and adding inputs based on bit values of filter coefficients. Minimum Signed Digit (MSD) representation of constants with Common Sub expression (CS) algorithms has been used to reduce the number of addition operations in filters for reducing dynamic power consumption. The proposed architecture has been designed using VHDL and simulated in ALTERA Quartus II 8.1. Experimental results demonstrates that the dynamic power dissipation of our MSD-CS multiplier is better compared to the previous designs and shows a delay reduction up to 17.2% compared to standard design. Design implementation of proposed multiplier in an18 tap FIR filter is done to verify its functionality.