Test Data Compression Architecture for Lowpower Vlsi Testing
B. Karthik, Anushpriya Selvaraj · 2014
2 Abstract: With the ever increasing integration capability of semiconductor technology, today's large integrated circuits requires an increasing amount of data for testing which increases test time and elevated requirements of tester memory. Larger test data sizes not only demand high memory requirements, but also a huge increase in the testing time. These remain the bottleneck for testing the whole system. The above disputes are addressed by the method called test data compression, which is reducing the test data volume without affecting the whole performance of the system. ISCAS'89 benchmark circuits are used to compress the test sets and the test vectors are generated by MINTEST vector generation. The main highlight of the paper is to reduce the test data volume and the test data memory by using coding schemes such as variable length coding, fixed length coding and so on.