Speed efficient implementation of round robin arbiter design using VERILOG
Ruma Deb · 2013
Round robin arbitration is commonly used for scheduling. With the revolutionary improvement in optical and electronics interconnection technologies, a very fast arbiter design is required to match the speed of high performance buses. This project present the design of high speed PPE arbiter the fairness of the arbiter is evaluated and possible enhancement to the arbiter. We show that our design is faster than existing round robin arbiter design. The main contribution of this project is the design of fast round robin arbiters. To make the arbiters fast, we first observe that a round-robin arbiter is equivalent to a programmable priority encoder, plus some state to store the round-robin pointer. A programmable priority encoder (PPE) differs from a simple priority encoder in that an external input dictates which input has the highest priority. In PPE arbiter design for each cycle, one of the masters (in round-robin order) has the highest priority (i.e., owns the token) for access to a shared resource. If the token- holding master does not need the resource in this cycle, the master with the next highest priority who sends a request can be granted the resource, and the highest priority master then passes the token to the next master in round-robin order.